We are excited to announce that we have now moved into fresh new offices on Barnet Road in St Albans. The new office is just a couple of miles from our old location. It provides more space, excellent access to the M25 and local amenities and there are three pubs within a stones throw of our door! The additional space will enable us to expand our services and take on additional staff as our business grows
It would be easy to fall into the trap of thinking we could simply replace our SD equipment with HD or Ultra HD equivalents and keep all our cabling infrastructure the same, but in practice it is not always so simple. As video resolution has increased from SD to HD to UltraHD, the SDI bit rate has increased dramatically from 270 Mb/s to 11.88 Gb/s, which in turn places increased demands on the cabling infrastructure that we use. In practical terms this greatly reduces the cable lengths that can be used, and some older or lower cost cables may not be usable at all.
I often find myself writing blocks of VHDL code (aka VHDL “components”) to process and manipulate MPEG transport streams. Once the component code is written, the next step is to simulate it to be sure it is functioning as intended. The usual approach is to write a “testbench” which is a further block of VHDL code that forms a “wrapper” around the component under test and feeds it with a variety of known and pre-programmed input stimuli.
Over the last few years I have been involved in the design of several digital television (DTV) transmitters and receivers. As you might expect. the bulk of the design effort on these projects is taken up in designing electronics, writing firmware and software and getting the mechanical packaging right. What may be less obvious however, is the huge effort involved in verifying that the design meets all the DTV standards and specifications.