Reading Transport Stream Files in VHDL
I often find myself writing blocks of VHDL code (aka VHDL “components”) to process and manipulate MPEG transport streams. Once the component code is written, the next step is to simulate it to be sure it is functioning as intended. The usual approach is to write a “testbench” which is a further block of VHDL code that forms a “wrapper” around the component under test and feeds it with a variety of known and pre-programmed input stimuli.
DVB Calculator
Over the last few years I have been involved in the design of several digital television (DTV) transmitters and receivers. As you might expect. the bulk of the design effort on these projects is taken up in designing electronics, writing firmware and software and getting the mechanical packaging right. What may be less obvious however, is the huge effort involved in verifying that the design meets all the DTV standards and specifications.